A path planning algorithm based on dynamic networks and restricted searching area M Fu, B Xue 2007 IEEE International Conference on Automation and Logistics, 1193-1197, 2007 | 24 | 2007 |
Minimizing back pressure for latency insensitive system synthesis B Xue, SK Shukla, SS Ravi Eighth ACM/IEEE International Conference on Formal Methods and Models for …, 2010 | 11 | 2010 |
Simplification of C-RTL equivalent checking for fused multiply add unit using intermediate models B Xue, P Chatterjee, SK Shukla 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 723-728, 2013 | 10 | 2013 |
Analysis of scheduled latency insensitive systems with periodic clock calculus B Xue, SK Shukla Journal of Electronic Testing 26 (2), 227-242, 2010 | 7 | 2010 |
Analysis of Scheduled Latency Insensitive Systems with Periodic Clock Calculus B Xue, SK Shukla IEEE International High Level Design Validation and Test Workshop, 1-7, 2009 | 7 | 2009 |
An analysis of the composition of synchronous systems BA Jose, B Xue, SK Shukla Electronic Notes in Theoretical Computer Science 245, 69-84, 2009 | 7 | 2009 |
Optimization of back pressure and throughput for latency insensitive systems B Xue, SK Shukla 2010 IEEE International Conference on Computer Design, 45-51, 2010 | 4 | 2010 |
Programming Models for Multi-Core Embedded Software BA Jose, B Xue, SK Shukla, JP Talpin Multi-Core embedded systems, 299-338, 2018 | 2 | 2018 |
Optimization of latency insensitive systems through back pressure minimization B Xue, SK Shukla, SS Ravi IEEE Transactions on Computers 64 (2), 464-476, 2013 | 2 | 2013 |
Modeling and analyzing the implementation of latency-insensitive protocols using the polychrony framework B Xue, SK Shukla Electronic Notes in Theoretical Computer Science 245, 3-22, 2009 | 1 | 2009 |
Cookie-Cutter Properties to Assist Non Formal Experts B Xue Jasper user group conference, 2014 | | 2014 |
Report on Polychrony Based Enabling Framework for Front-to-back Formal Flow and Its Capabilities for Specification of GALS Based IP Composition, Mapping to Circuit Elements and … S Shukla, B Xue, K Stevens https://www.src.org/library/publication/p062791/, 2012 | | 2012 |
Formal Approaches to Specification, Analysis and Design Framework for Globally Asynchronous Composition of Locally Synchronous Cores S Shukla, K Stevens, B Xue https://www.src.org/library/publication/p061651/, 2011 | | 2011 |
Formal Approaches to Globally Asynchronous and Locally Synchronous Design B Xue Virginia Tech, 2011 | | 2011 |
Report on Desynchronization Techniques, Protocol Insertion, and Protocol Mapping to Implementable Circuit Elements, B Xue, SK Shukla, K Stevens https://www.src.org/library/publication/p055785/, 2010 | | 2010 |
Progress Report on Polychrony Based Framework for GALS and LIP Composition, Methodology Description, and Algorithms for Decomposition, SK Shukla, B Xue https://www.src.org/library/publication/p051686/, 2009 | | 2009 |