| hXDP: Efficient software packet processing on FPGA NICs MS Brunella, G Belocchi, M Bonola, S Pontarelli, G Siracusano, G Bianchi, ... Communications of the ACM 65 (8), 92-100, 2022 | 81 | 2022 |
| A lightweight security checking module to protect microprocessors against hardware trojan horses A Palumbo, L Cassano, P Reviriego, G Bianchi, M Ottavi 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2021 | 11 | 2021 |
| Processor security: Detecting microarchitectural attacks via count-min sketches K Arıkan, A Palumbo, L Cassano, P Reviriego, S Pontarelli, G Bianchi, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (7), 938-951, 2022 | 10 | 2022 |
| Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer A Palumbo, L Cassano, B Luzzi, JA Hernández, P Reviriego, G Bianchi, ... Journal of Systems Architecture 128, 102543, 2022 | 9 | 2022 |
| Is risc-v ready for space? a security perspective L Cassano, S Di Mascio, A Palumbo, A Menicucci, G Furano, G Bianchi, ... 2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2022 | 8 | 2022 |
| hXDP: efficient software packet processing on FPGA NICs M Spaziani Brunella, G Belocchi, M Bonola, S Pontarelli, G Siracusano, ... arXiv e-prints, arXiv: 2010.14145, 2020 | 7 | 2020 |
| Towards dependable RISC-V cores for edge computing devices PR Nikiema, A Palumbo, A Aasma, L Cassano, A Kritikakou, A Kulmala, ... 2023 IEEE 29th International Symposium on On-Line Testing and Robust System …, 2023 | 2 | 2023 |
| Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses A Palumbo, M Ottavi, L Cassano 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2023 | | 2023 |
| Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes A Palumbo, L Cassano, P Reviriego, M Ottavi 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2023 | | 2023 |
| Machine Learning-Based Classification of Hardware Trojans in FPGAs Implementing RISC-V Cores S Ribes, F Malatesta, G Garzo, A Palumbo | | |
