High-level language tools for reconfigurable computing S Windh, X Ma, RJ Halstead, P Budhkar, Z Luna, O Hussaini, WA Najjar Proceedings of the IEEE 103 (3), 390-408, 2015 | 97 | 2015 |
An open-source compiler and PCB synthesis tool for digital microfluidic biochips D Grissom, C Curtis, S Windh, C Phung, N Kumar, Z Zimmerman, ... INTEGRATION, the VLSI journal 51, 169-193, 2015 | 71 | 2015 |
FPGA-accelerated group-by aggregation using synchronizing caches I Absalyamov, P Budhkar, S Windh, RJ Halstead, WA Najjar, VJ Tsotras Proceedings of the 12th International Workshop on Data Management on New …, 2016 | 26 | 2016 |
Performance improvements and congestion reduction for routing-based synthesis for digital microfluidic biochips S Windh, C Phung, DT Grissom, P Pop, P Brisk IEEE transactions on computer-aided design of integrated circuits and …, 2016 | 26 | 2016 |
CAMs as synchronizing caches for multithreaded irregular applications on FPGAs S Windh, P Budhkar, WA Najjar 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 331-336, 2015 | 7 | 2015 |
Accelerating in-memory database selections using latency masking hardware threads P Budhkar, I Absalyamov, V Zois, S Windh, WA Najjar, VJ Tsotras ACM Transactions on Architecture and Code Optimization (TACO) 16 (2), 1-28, 2019 | 6 | 2019 |
Reinforcement Learning Approach for Mapping Applications to Dataflow-Based Coarse-Grained Reconfigurable Array AXM Chang, P Khopkar, B Romanous, A Chaurasia, P Estep, S Windh, ... arXiv preprint arXiv:2205.13675, 2022 | 4 | 2022 |
Mask field propagation among memory-compute tiles in a reconfigurable architecture B Hornung, SA Windh US Patent 11,782,725, 2023 | 2 | 2023 |
Debugging dataflow computer architectures SA Windh, TM Brewer, P Estep US Patent 11,507,493, 2022 | 2 | 2022 |
Efficient local locking for massively multithreaded in-memory hash-based operators B Romanous, S Windh, I Absalyamov, P Budhkar, R Halstead, W Najjar, ... The VLDB Journal 30 (3), 333-359, 2021 | 2 | 2021 |
Packing conditional branch operations SA Windh, G Wang US Patent 11,604,650, 2023 | 1 | 2023 |
Mechanism to trigger early termination of cooperating processes P Estep, SA Windh, TM Brewer US Patent 11,550,642, 2023 | 1 | 2023 |
Dynamic decomposition and thread allocation SA Windh, TM Brewer, P Estep US Patent App. 17/465,021, 2022 | 1 | 2022 |
Hashing, Caching, and Synchronization: Memory Techniques for Latency Masking Multithreaded Applications SA Windh University of California, Riverside, 2018 | 1 | 2018 |
Packing conditional branch operations SA Windh, G Wang US Patent 11,829,758, 2023 | | 2023 |
Programming a coarse grained reconfigurable array through description of data flow graphs SA Windh, AK Porterfield, DJ Vanesko, RP Meyer, PA Estep, B Romanous US Patent 11,815,935, 2023 | | 2023 |
Mechanism to trigger early termination of cooperating processes P Estep, SA Windh, TM Brewer US Patent 11,789,790, 2023 | | 2023 |
Configure a Coarse Grained Reconfigurable Array to Execute Instructions of a Program of Data Flows SA Windh, DJ Vanesko US Patent App. 17/705,091, 2023 | | 2023 |
Mapping Workloads to Circuit Units in a Computing Device via Reinforcement Learning AXM Chang, A Chaurasia, P Khopkar, B Romanous, PA Estep, SA Windh, ... US Patent App. 18/185,031, 2023 | | 2023 |
Schedule Instructions of a Program of Data Flows for Execution in Tiles of a Coarse Grained Reconfigurable Array AK Porterfield, SA Windh, B Romanous US Patent App. 17/705,112, 2023 | | 2023 |