| Molecular electronics: From devices and interconnect to circuits and architecture MR Stan, PD Franzon, SC Goldstein, JC Lach, MM Ziegler Proceedings of the IEEE 91 (11), 1940-1957, 2003 | 374 | 2003 |
| CMOS/nano co-design for crossbar-based molecular electronic systems MM Ziegler, MR Stan IEEE Transactions on Nanotechnology 2 (4), 217-230, 2003 | 247 | 2003 |
| A Scalable Multi-TeraOPS Deep Learning Processor Core for AI Trainina and Inference B Fleischer, S Shukla, M Ziegler, J Silberman, J Oh, V Srinivasan, J Choi, ... 2018 IEEE Symposium on VLSI Circuits, 35-36, 2018 | 154 | 2018 |
| A sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing AJ Bhavnagarwala, S Kosonocky, C Radens, Y Chan, K Stawiasz, ... IEEE Journal of Solid-State Circuits 43 (4), 946-955, 2008 | 144 | 2008 |
| Design and analysis of crossbar circuits for molecular nanoelectronics MM Ziegler, MR Stan Proceedings of the 2nd IEEE Conference on Nanotechnology, 323-327, 2002 | 127 | 2002 |
| 5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth EJ Fluhr, J Friedrich, D Dreps, V Zyuban, G Still, C Gonzalez, A Hall, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 120 | 2014 |
| RaPiD: AI accelerator for ultra-low precision training and inference S Venkataramani, V Srinivasan, W Wang, S Sen, J Zhang, A Agrawal, ... 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 88 | 2021 |
| 9.1 a 7nm 4-core AI chip with 25.6 TFLOPS hybrid FP8 training, 102.4 TOPS INT4 inference and workload-aware throttling A Agrawal, SK Lee, J Silberman, M Ziegler, M Kang, S Venkataramani, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 144-146, 2021 | 85 | 2021 |
| Relative ordering circuit synthesis M Cho, R Puri, H Ren, X Tang, H Xiang, MM Ziegler US Patent 8,756,541, 2014 | 83 | 2014 |
| Relative ordering circuit synthesis M Cho, R Puri, H Ren, X Tang, H Xiang, MM Ziegler US Patent 8,756,541, 2014 | 83 | 2014 |
| Specifying circuit level connectivity during circuit design synthesis MD Amundson, D Kucar, R Puri, CN Sze, MM Ziegler US Patent 8,839,162, 2014 | 64 | 2014 |
| Specifying circuit level connectivity during circuit design synthesis MD Amundson, D Kucar, R Puri, CN Sze, MM Ziegler US Patent 8,839,162, 2014 | 64 | 2014 |
| Resilient Low Voltage Accelerators for High Energy Efficiency N Chandramoorthy, K Swaminathan, M Cochet, A Paidimarri, S Eldridge, ... 2019 IEEE International Symposium on High Performance Computer Architecture …, 2019 | 60 | 2019 |
| Efficient AI system design with cross-layer approximate computing S Venkataramani, X Sun, N Wang, CY Chen, J Choi, M Kang, A Agarwal, ... Proceedings of the IEEE 108 (12), 2232-2250, 2020 | 57 | 2020 |
| Converged large block and structured synthesis for high performance microprocessor designs M Cho, VN Kravets, S Krishnaswamy, D Kucar, J Narasimhan, R Puri, ... US Patent 8,271,920, 2012 | 53 | 2012 |
| Converged large block and structured synthesis for high performance microprocessor designs M Cho, VN Kravets, S Krishnaswamy, D Kucar, J Narasimhan, R Puri, ... US Patent 8,271,920, 2012 | 53 | 2012 |
| A synthesis-parameter tuning system for autonomous design-space exploration MM Ziegler, HY Liu, G Gristede, B Owens, R Nigaglioni, LP Carloni 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 52 | 2016 |
| A case for CMOS/nano co-design MM Ziegler, MR Stan Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002 | 50 | 2002 |
| A case for CMOS/nano co-design MM Ziegler, MR Stan Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002 | 50 | 2002 |
| A 3.0 TFLOPS 0.62 V Scalable Processor Core for High Compute Utilization AI Training and Inference J Oh, SK Lee, M Kang, M Ziegler, J Silberman, A Agrawal, ... 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 44 | 2020 |
