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Qingan Li
Qingan Li
Computer School, Wuhan University
Verified email at whu.edu.cn
Title
Cited by
Cited by
Year
Compiler-assisted STT-RAM-based hybrid cache for energy efficient embedded systems
Q Li, J Li, L Shi, M Zhao, CJ Xue, Y He
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (8 …, 2013
512013
Compiler-assisted refresh minimization for volatile STT-RAM cache
Q Li, Y He, J Li, L Shi, Y Chen, CJ Xue
IEEE Transactions on Computers 64 (8), 2169-2181, 2014
472014
Software assisted non-volatile register reduction for energy harvesting based cyber-physical system
M Zhao, Q Li, M Xie, Y Liu, J Hu, CJ Xue
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 567-572, 2015
452015
MAC: Migration-aware compilation for STT-RAM based hybrid cache in embedded systems
Q Li, J Li, L Shi, CJ Xue, Y He
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
422012
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh
J Li, L Shi, Q Li, CJ Xue, Y Chen, Y Xu, W Wang
ACM Transactions on Design Automation of Electronic Systems (TODAES) 19 (1 …, 2013
342013
Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache
Q Li, M Zhao, CJ Xue, Y He
Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on …, 2012
342012
Compiler directed automatic stack trimming for efficient non-volatile processors
Q Li, M Zhao, J Hu, Y Liu, Y He, CJ Xue
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
322015
Stack-size sensitive on-chip memory backup for self-powered nonvolatile processors
M Zhao, C Fu, Z Li, Q Li, M Xie, Y Liu, J Hu, Z Jia, CJ Xue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
312017
A spatio-temporal sequence-to-sequence network for traffic flow prediction
S Cao, L Wu, J Wu, D Wu, Q Li
Information Sciences 610, 185-203, 2022
302022
Compiler directed write-mode selection for high performance low power volatile PCM
Q Li, L Jiang, Y Zhang, Y He, CJ Xue
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages …, 2013
292013
A wear leveling aware memory allocator for both stack and heap management in pcm-based main memory systems
W Li, Z Shuai, CJ Xue, M Yuan, Q Li
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 228-233, 2019
272019
Cache coherence enabled adaptive refresh for volatile STT-RAM
J Li, L Shi, CJ Xue, Y Chen, Y Xu
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013
222013
Task offloading with task classification and offloading nodes selection for MEC-enabled IoV
R Zhang, L Wu, S Cao, X Hu, S Xue, D Wu, Q Li
ACM Transactions on Internet Technology (TOIT) 22 (2), 1-24, 2021
192021
Task allocation on nonvolatile-memory-based hybrid main memory
W Tian, Y Zhao, L Shi, Q Li, J Li, CJ Xue, M Li, E Chen
IEEE transactions on very large scale integration (VLSI) systems 21 (7 …, 2012
192012
A mobile edge computing-based applications execution framework for Internet of Vehicles
L Wu, R Zhang, Q Li, C Ma, X Shi
Frontiers of Computer Science 16 (5), 165506, 2022
182022
A wear-leveling-aware dynamic stack for PCM memory in embedded systems
Q Li, Y He, Y Chen, CJ Xue, N Jiang, C Xu
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
182014
MGC: Multiple Graph-Coloring for Non-Volatile Memory Based Hybrid Scratchpad Memory
Q Li, Y Zhao, J Hu, CJ Xue, E Sha, Y He
Proc. INTERACT 16, 1-6, 2012
162012
Migration-aware loop retiming for STT-RAM-based hybrid cache in embedded systems
K Qiu, M Zhao, Q Li, C Fu, CJ Xue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
122014
Write mode aware loop tiling for high performance low power volatile PCM
K Qiu, Q Li, CJ Xue
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
112014
A unified write buffer cache management scheme for flash memory
L Shi, J Li, Q Li, CJ Xue, C Yang, X Zhou
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (12 …, 2014
112014
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Articles 1–20