| Suggesting emoji characters based on current contextual emotional state of user S Liu, EJ Rozner, CN Sze, Y Wei US Patent 9,665,567, 2017 | 180 | 2017 |
| The DAC 2012 routability-driven placement contest and benchmark suite N Viswanathan, C Alpert, C Sze, Z Li, Y Wei Proceedings of the 49th Annual Design Automation Conference, 774-782, 2012 | 132 | 2012 |
| The ISPD-2011 routability-driven placement contest and benchmark suite N Viswanathan, CJ Alpert, C Sze, Z Li, GJ Nam, JA Roy Proceedings of the 2011 international symposium on Physical design, 141-146, 2011 | 124 | 2011 |
| GLARE: Global and local wiring aware routability evaluation Y Wei, C Sze, N Viswanathan, Z Li, CJ Alpert, L Reddy, AD Huber, ... Proceedings of the 49th Annual Design Automation Conference, 768-773, 2012 | 103 | 2012 |
| Fast algorithms for slew constrained minimum cost buffering S Hu, CJ Alpert, J Hu, S Karandikar, Z Li, W Shi, CN Sze Proceedings of the 43rd annual Design Automation Conference, 308-313, 2006 | 102 | 2006 |
| Techniques for fast physical synthesis CJ Alpert, SK Karandikar, Z Li, GJ Nam, ST Quay, H Ren, CN Sze, ... Proceedings of the IEEE 95 (3), 573-599, 2007 | 85 | 2007 |
| ISPD 2010 high performance clock network synthesis contest: Benchmark suite and results CN Sze Proceedings of the 19th international symposium on Physical design, 143-143, 2010 | 83 | 2010 |
| Specifying circuit level connectivity during circuit design synthesis MD Amundson, D Kucar, R Puri, CN Sze, MM Ziegler US Patent 8,839,162, 2014 | 62 | 2014 |
| Large-scale 3D chips: Challenges and solutions for design automation, testing, and trustworthy integration J Knechtel, O Sinanoglu, IAM Elfadel, J Lienig, CCN Sze IPSJ Transactions on System and LSI Design Methodology 10, 45-62, 2017 | 58 | 2017 |
| The ISPD global routing benchmark suite GJ Nam, C Sze, M Yildiz Proceedings of the 2008 international symposium on Physical design, 156-159, 2008 | 58 | 2008 |
| Accurate estimation of global buffer delay within a floorplan CJ Alpert, J Hu, SS Sapatnekar, CN Sze IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006 | 58 | 2006 |
| Converged large block and structured synthesis for high performance microprocessor designs M Cho, VN Kravets, S Krishnaswamy, D Kucar, J Narasimhan, R Puri, ... US Patent 8,271,920, 2012 | 52 | 2012 |
| ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite N Viswanathan, C Alpert, C Sze, Z Li, Y Wei Proceedings of the International Conference on Computer-Aided Design, 345-348, 2012 | 51 | 2012 |
| RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm DA Papa, T Luo, MD Moffitt, CN Sze, Z Li, GJ Nam, CJ Alpert, IL Markov Proceedings of the 2008 international symposium on Physical design, 2-9, 2008 | 51 | 2008 |
| Navigating registers in placement for clock network minimization Y Lu, CN Sze, X Hong, Q Zhou, Y Cai, L Huang, J Hu Proceedings of the 42nd annual Design Automation Conference, 176-181, 2005 | 51 | 2005 |
| Physical synthesis with clock-network optimization for large systems on chips D Papa, C Alpert, C Sze, Z Li, N Viswanathan, GJ Nam, I Markov IEEE Micro 31 (4), 51-62, 2011 | 50 | 2011 |
| ISPD2009 clock network synthesis contest CN Sze, P Restle, GJ Nam, C Alpert Proceedings of the 2009 International Symposium on Physical design, 149-150, 2009 | 48 | 2009 |
| Latch placement for high performance and low power circuits CJ Alpert, S Ramji, CN Sze, PG Villarrubia US Patent 7,549,137, 2009 | 47 | 2009 |
| Path based buffer insertion CN Sze, CJ Alpert, J Hu, W Shi Proceedings of the 42nd annual Design Automation Conference, 509-514, 2005 | 47 | 2005 |
| Timing-driven steiner trees are (practically) free CJ Alpert, AB Kahng, CN Sze, Q Wang Proceedings of the 43rd annual Design Automation Conference, 389-392, 2006 | 41 | 2006 |
Chuck AlpertFellow, Cadence Design SystemsVerified email at cadence.com
