Sandip Ray

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Swarup BhuniaUniversity of FloridaVerified email at ece.ufl.edu
Abhishek BasakResearch Scientist, Intel Labs, Intel CorporationVerified email at intel.com
Fei XieDepartment of Computer Science, Portland State UniversityVerified email at cs.pdx.edu
Yier JinAssociate Professor, University of FloridaVerified email at ece.ufl.edu
jstrother mooreComputer Science Dept, University of Texas at AustinVerified email at cs.utexas.edu
Prabhat MishraProfessor, Univ. of Florida, IEEE Fellow, AAAS Fellow, ACM Distinguished MemberVerified email at ufl.edu
Atul Prasad Deb NathQualcomm Technologies, Inc.Verified email at qti.qualcomm.com
Srivalli BoddupalliUniversity of FloridaVerified email at ufl.edu
Mark M. TehranipoorIntel Charles E. Young Endowed Chair Professor, ECE, University of FloridaVerified email at ufl.edu
Rosario Cammarota ("Ro")Intel LabsVerified email at ieee.org
Nikil DuttDistinguished Professor, CS, EECS & Cognitive Sciences, University of California, IrvineVerified email at uci.edu
Warren A. Hunt, JrProfessor of Computer Science, University of TexasVerified email at cs.utexas.edu
Jin YangIntel CorporationVerified email at intel.com
Tamzidul HoqueAssistant Professor of EECS, University of KansasVerified email at ku.edu
Hamid NejatollahiUniversity of California IrvineVerified email at uci.edu
Francesco RegazzoniUniversity of Amsterdam and Università della Svizzera italianaVerified email at alari.ch
Kamran RahmaniUniversity of FloridaVerified email at cise.ufl.edu
Zhenkun YangPortland State UniversityVerified email at cs.pdx.edu
Li-C. WangUniversity of California, Santa BarbaraVerified email at ece.ucsb.edu
Robert KaramAssistant Professor of CSE, University of South FloridaVerified email at usf.edu

Sandip Ray

Professor, Department of Electrical and Computer Engineering, University of Florida at Gainesville

Verified email at ece.ufl.edu - Homepage

Internet of Things Security Low-power design Design validation Formal methods


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Post-quantum lattice-based cryptography implementations: A survey H Nejatollahi, N Dutt, S Ray, F Regazzoni, I Banerjee, R Cammarota ACM Computing Surveys (CSUR) 51 (6), 1-41, 2019	165	2019
Internet-of-Things security and vulnerabilities: Taxonomy, challenges, and practice K Chen, S Zhang, Z Li, Y Zhang, Q Deng, S Ray, Y Jin Journal of Hardware and Systems Security 2, 97-110, 2018	156	2018
The changing computing paradigm with internet of things: A tutorial introduction S Ray, Y Jin, A Raychowdhury IEEE Design & Test 33 (2), 76-96, 2016	133	2016
A survey of hybrid techniques for functional verification J Bhadra, MS Abadir, LC Wang, S Ray IEEE Design & Test of Computers 24 (02), 112-122, 2007	90	2007
Challenges and trends in modern SoC design verification W Chen, S Ray, J Bhadra, M Abadir, LC Wang IEEE Design & Test 34 (5), 7-22, 2017	83	2017
System-on-chip platform security assurance: Architecture and validation S Ray, E Peeters, MM Tehranipoor, S Bhunia Proceedings of the IEEE 106 (1), 21-37, 2017	66	2017
Security assurance for system-on-chip designs with untrusted IPs A Basak, S Bhunia, T Tkacik, S Ray IEEE Transactions on Information Forensics and Security 12 (7), 1515-1528, 2017	64	2017
Post-silicon validation in the SoC era: A tutorial introduction P Mishra, R Morad, A Ziv, S Ray IEEE Design & Test 34 (3), 68-92, 2017	62	2017
Efficient trace signal selection using augmentation and ILP techniques K Rahmani, P Mishra, S Ray Fifteenth international symposium on quality electronic design, 148-155, 2014	62	2014
Verification condition generation via theorem proving J Matthews, JS Moore, S Ray, D Vroon Logic for Programming, Artificial Intelligence, and Reasoning: 13th …, 2006	58	2006
A flexible architecture for systematic implementation of SoC security policies A Basak, S Bhunia, S Ray 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 536-543, 2015	53	2015
Robust bitstream protection in FPGA-based systems through low-overhead obfuscation R Karam, T Hoque, S Ray, M Tehranipoor, S Bhunia 2016 International Conference on ReConFigurable Computing and FPGAs …, 2016	45	2016
Can't see the forest for the trees: State restoration's limitations in post-silicon trace signal selection S Ma, D Pal, R Jiang, S Ray, S Vasudevan 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2015	45	2015
Deductive verification of pipelined machines using first-order quantification S Ray, WA Hunt Computer Aided Verification: 16th International Conference, CAV 2004, Boston …, 2004	43	2004
Efficient execution in an automated reasoning environment DA Greve, M Kaufmann, P Manolios, JS Moore, S Ray, JL Ruiz-Reina, ... Journal of Functional Programming 18 (1), 15-46, 2008	41	2008
Exploiting design-for-debug for flexible SoC security architecture A Basak, S Bhunia, S Ray Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016	37	2016
Optimizing equivalence checking for behavioral synthesis K Hao, F Xie, S Ray, J Yang 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010	37	2010
Correctness and security at odds: post-silicon validation of modern SoC designs S Ray, J Yang, A Basak, S Bhunia Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015	36	2015
Scalable techniques for formal verification S Ray Springer Science & Business Media, 2010	35	2010
Security policy enforcement in modern SoC designs S Ray, Y Jin 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 345-350, 2015	32	2015

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