| High-performance symmetric-gate and CMOS-compatible V/sub t/asymmetric-gate FinFET devices J Kedzierski, DM Fried, EJ Nowak, T Kanarsky, JH Rankin, H Hanafi, ... International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 286 | 2001 |
| Method of fabricating a FinFET BA Anderson, EJ Nowak, JH Rankin US Patent 7,247,908, 2007 | 258 | 2007 |
| Fin field effect transistor with self-aligned gate JP Gambino, JB Lasky, JH Rankin US Patent 6,689,650, 2004 | 255 | 2004 |
| Device and design structures for memory cells in a non-volatile random access memory and methods of fabricating such device structures WW Abadeer, KV Chatty, RJ Gauthier Jr, JH Rankin, Y Shi, WR Tonti US Patent 7,790,524, 2010 | 226 | 2010 |
| Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same DM Fried, TJ Hoague, EJ Nowak, JH Rankin US Patent 6,583,469, 2003 | 212 | 2003 |
| Method to define and tailor process limited lithographic features using a modified hard mask process DS Armbrust, DW Martin, JH Rankin, S Tousley US Patent 6,610,607, 2003 | 204 | 2003 |
| Double planar gated SOI MOSFET structure JW Adkisson, JA Bracchitta, JJ Ellis-Monaghan, JB Lasky, E Leobandung, ... US Patent 6,483,156, 2002 | 203 | 2002 |
| Circuit layout methodology using a shape processing application JM Cohn, J Hibbeler, AK Stamper, JH Rankin US Patent 7,188,322, 2007 | 199 | 2007 |
| Nitride etch for improved spacer uniformity JA Culp, JJ Ellis-Monaghan, JP Gambino, KD Peterson, JH Rankin, ... US Patent 8,470,713, 2013 | 140 | 2013 |
| Concurrent Fin-FET and thick-body device fabrication WW Abadeer, JS Brown, DM Fried, RJ Gauthier Jr, EJ Nowak, JH Rankin, ... US Patent 7,163,851, 2007 | 133 | 2007 |
| Double gate trench transistor JW Adkisson, PD Agnello, AW Ballantine, R Divakaruni, EC Jones, ... US Patent 6,472,258, 2002 | 120 | 2002 |
| Double gated transistor and method of fabrication A Bryant, M Ieong, KP Muller, EJ Nowak, DM Fried, J Rankin US Patent 7,288,445, 2007 | 117 | 2007 |
| Implanted asymmetric doped polysilicon gate FinFET DM Fried, EJ Nowak, JH Rankin US Patent 6,800,905, 2004 | 113 | 2004 |
| IEDM Tech J Kedzierski, DM Fried, EJ Nowak, T Kanarsky, JH Rankin, H Hanafi, ... Dig 247 (441), 2003, 2002 | 113 | 2002 |
| Integrated antifuse structure for FINFET and CMOS devices JH Rankin, WW Abadeer, JS Brown, WR Tonti US Patent 7,087,499, 2006 | 106 | 2006 |
| Method and structure to create multiple device widths in FinFET technology in both bulk and SOI BA Anderson, EJ Nowak, JH Rankin US Patent 7,224,029, 2007 | 101 | 2007 |
| Vertical trench-formed dual-gate FET device structure and method for creation PD Agnello, AW Ballantine, R Divakaruni, EC Jones, EJ Nowak, ... US Patent 6,406,962, 2002 | 94 | 2002 |
| Method and structure to process thick and thin fins and variable fin to fin spacing WW Abadeer, JS Brown, KV Chatty, RJ Gauthler Jr, JH Rankin, WR Tonti US Patent 7,763,531, 2010 | 91 | 2010 |
| Planar substrate devices integrated with finfets and method of manufacture BA Anderson, EJ Nowak, JH Rankin US Patent 6,949,768, 2005 | 90 | 2005 |
| Body contact MOSFET A Bryant, PE Cottrell, JJ Ellis-Monaghan, RJ Gauthier Jr, EJ Nowak, ... US Patent 6,677,645, 2004 | 88 | 2004 |
Brent AndersonSenior Staff Engineer at IBMVerified email at us.ibm.com
