Debjyoti Bhattacharjee
Debjyoti Bhattacharjee
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ReVAMP: ReRAM based VLIW architecture for in-memory computing
D Bhattacharjee, R Devadoss, A Chattopadhyay
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
SIMPLER MAGIC: Synthesis and mapping of in-memory logic executed in a single row to improve throughput
R Ben-Hur, R Ronen, A Haj-Ali, D Bhattacharjee, A Eliahu, N Peled, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
Depth-optimal quantum circuit placement for arbitrary topologies
D Bhattacharjee, A Chattopadhyay
arXiv preprint arXiv:1703.08540, 2017
MUQUT: Multi-constraint quantum circuit mapping on NISQ computers
D Bhattacharjee, AA Saki, M Alam, A Chattopadhyay, S Ghosh
2019 IEEE/ACM international conference on computer-aided design (ICCAD), 1-7, 2019
DIANA: An end-to-end energy-efficient digital and ANAlog hybrid neural network SoC
K Ueyoshi, IA Papistas, P Houshmand, GM Sarda, V Jain, M Shi, Q Zheng, ...
2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022
Multi-valued and fuzzy logic realization using TaOx memristive devices
D Bhattacharjee, W Kim, A Chattopadhyay, R Waser, V Rana
Scientific reports 8 (1), 8, 2018
Diana: An end-to-end hybrid digital and analog neural network soc for the edge
P Houshmand, GM Sarda, V Jain, K Ueyoshi, IA Papistas, M Shi, Q Zheng, ...
IEEE Journal of Solid-State Circuits 58 (1), 203-215, 2022
Techniques for fault-tolerant decomposition of a multicontrolled Toffoli gate
L Biswal, D Bhattacharjee, A Chattopadhyay, H Rahaman
Physical Review A 100 (6), 062326, 2019
Quantum circuits for Toom-Cook multiplication
S Dutta, D Bhattacharjee, A Chattopadhyay
Physical Review A 98 (1), 012311, 2018
Opportunities and limitations of emerging analog in-memory compute DNN architectures
P Houshmand, S Cosemans, L Mei, I Papistas, D Bhattacharjee, ...
2020 IEEE International Electron Devices Meeting (IEDM), 29.1. 1-29.1. 4, 2020
Sklansky tree adder realization in 1S1R resistive switching memory architecture
A Siemon, S Menzel, D Bhattacharjee, R Waser, A Chattopadhyay, E Linn
The European Physical Journal Special Topics 228, 2269-2285, 2019
Efficient complementary resistive switch-based crossbar array booth multiplier
D Bhattacharjee, A Siemon, E Linn, A Chattopadhyay
Microelectronics Journal 64, 78-85, 2017
SAID: A supergate-aided logic synthesis flow for memristive crossbars
V Tenace, RG Rizzo, D Bhattacharjee, A Chattopadhyay, A Calimera
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 372-377, 2019
Delay-optimal technology mapping for in-memory computing using ReRAM devices
D Bhattacharjee, A Chattopadhyay
2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2016
Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays
D Bhattacharjee, F Merchant, A Chattopadhyay
2016 IFIP/IEEE International Conference on Very Large Scale Integration …, 2016
Contra: area-constrained technology mapping framework for memristive memory processing unit
D Bhattacharjee, A Chattopadhyay, S Dutta, R Ronen, S Kvatinsky
Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020
Crossbar-constrained technology mapping for ReRAM based in-memory computing
D Bhattacharjee, Y Tavva, A Easwaran, A Chattopadhyay
IEEE Transactions on Computers 69 (5), 734-748, 2020
Technology-aware logic synthesis for ReRAM based in-memory computing
D Bhattacharjee, L Amaŕu, A Chattopadhyay
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
SHA-3 implementation using ReRAM based in-memory computing architecture
D Bhattacharjee, V Pudi, A Chattopadhyay
2017 18th International Symposium on Quality Electronic Design (ISQED), 325-330, 2017
Design-technology space exploration for energy efficient AiMC-based inference acceleration
D Bhattacharjee, N Laubeuf, S Cosemans, I Papistas, A Maliik, ...
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021
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