Vishwani Agrawal
Vishwani Agrawal
professor of electrical engineering
Verified email at
Cited by
Cited by
Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits
M Bushnell, V Agrawal
Springer Science & Business Media, 2004
A tutorial on built-in self-test. I. Principles
VD Agrawal, CR Kime, KK Saluja
IEEE Design & Test of Computers 10 (1), 73-82, 1993
A partial scan method for sequential circuits with feedback
KT Cheng, VD Agrawal
IEEE Transactions on Computers 39 (4), 544-548, 1990
Scheduling tests for VLSI systems under power constraints
RM Chou, KK Saluja, VD Agrawal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5 (2), 175-185, 1997
Chip layout optimization using critical path weighting
AE Dunlop, VD Agrawal, DN Deutsch, MF Jukl, P Kazak
Papers on Twenty-five years of electronic design automation, 278-281, 1988
Single event upset: An embedded tutorial
F Wang, VD Agrawal
21st International Conference on VLSI Design (VLSID 2008), 429-434, 2008
PREDICT: Probabilistic estimation of digital circuit testability
SC Seth
Proc. 15th Int. Fault-Tolerant Computer Symp., 220-225, 1985
A transitive closure algorithm for test generation
ST Chakradhar, VD Agrawal, SG Rothweiler
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1993
An exact algorithm for selecting partial scan flip-flops
ST Chakradhar, A Balakrishnan, VD Agrawal
Proceedings of the 31st annual Design Automation Conference, 81-86, 1994
Statistical fault analysis
SK Jain, VD Agrawal
IEEE Design & Test of Computers 2 (1), 38-44, 1985
Robust tests for stuck-open faults in CMOS combinational logic circuits
SM Reddy, MK Reddy, VD Agrawal
Proc. Int. Symp. on Fault-Tolerant Computing, 44-49, 1984
Test generation for MOS circuits using D-algorithm
SK Jain, VD Agrawal
20th Design Automation Conference Proceedings, 64-70, 1983
Designing circuits with partial scan
VD Agrawal, KT Cheng, DD Johnson, TS Lin
IEEE Design & Test of Computers 5 (2), 8-15, 1988
Tutorial test generation for VLSI chips
VD Agrawal, SC Seth
(No Title), 1988
Fault coverage requirement in production testing of LSI circuits
VD Agrawal, SC Seth, P Agrawal
IEEE Journal of Solid-State Circuits 17 (1), 57-61, 1982
Segment delay faults: A new fault model
K Heragu, JH Patel, VD Agrawal
Proceedings of 14th VLSI Test Symposium, 32-39, 1996
Sampling techniques for determining fault coverage in LSI circuits
VD Agrawal
Journal of Digital Systems 5 (3), 189-202, 1981
STAFAN: An alternative to fault simulation
SK Jain, VD Agrawal
Papers on Twenty-five years of electronic design automation, 475-480, 1988
Classification and test generation for path-delay faults using single struck-at fault tests
MA Gharaybeh, ML Bushnell, VD Agrawal
Journal of Electronic Testing 11, 55-67, 1997
Delay fault models and test generation for random logic sequential circuits
TJ Chakraborty, VD Agrawal, ML Bushnell
Annual ACM IEEE Design Automation Conference: Proceedings of the 29 th ACM …, 1992
The system can't perform the operation now. Try again later.
Articles 1–20