Jeyavijayan (JV) Rajendran
Jeyavijayan (JV) Rajendran
Other namesJeyavijayan Rajendran, JV Rajendran
Associate Professor of Electrical and Computer Engineering, Texas A&M University
Verified email at - Homepage
Cited by
Cited by
Trustworthy hardware: Identifying and classifying hardware trojans
R Karri, J Rajendran, K Rosenfeld, M Tehranipoor
Computer 43 (10), 39-46, 2010
Security analysis of logic obfuscation
J Rajendran, Y Pino, O Sinanoglu, R Karri
Proceedings of the 49th annual design automation conference, 83-89, 2012
Fault analysis-based logic encryption
J Rajendran, H Zhang, C Zhang, GS Rose, Y Pino, O Sinanoglu, R Karri
IEEE Transactions on computers 64 (2), 410-424, 2013
Security analysis of integrated circuit camouflaging
J Rajendran, M Sam, O Sinanoglu, R Karri
Proceedings of the 2013 ACM SIGSAC conference on Computer & communications …, 2013
SARLock: SAT attack resistant logic locking
M Yasin, B Mazumdar, JJV Rajendran, O Sinanoglu
2016 IEEE International Symposium on Hardware Oriented Security and Trust …, 2016
On improving the security of logic locking
M Yasin, JJV Rajendran, O Sinanoglu, R Karri
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015
Provably-secure logic locking: From theory to practice
M Yasin, A Sengupta, MT Nabeel, M Ashraf, J Rajendran, O Sinanoglu
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications …, 2017
Manufacturing and security challenges in 3D printing
SE Zeltmann, N Gupta, NG Tsoutsos, M Maniatakos, J Rajendran, R Karri
Jom 68 (7), 1872-1881, 2016
Removal attacks on logic locking and camouflaging techniques
M Yasin, B Mazumdar, O Sinanoglu, J Rajendran
IEEE Transactions on Emerging Topics in Computing 8 (2), 517-532, 2017
Is split manufacturing secure?
J Rajendran, O Sinanoglu, R Karri
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013
Security analysis of anti-sat
M Yasin, B Mazumdar, O Sinanoglu, J Rajendran
2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 342-347, 2017
Logic encryption: A fault analysis perspective
J Rajendran, Y Pino, O Sinanoglu, R Karri
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 953-958, 2012
Hardware security: Threat models and metrics
M Rostami, F Koushanfar, J Rajendran, R Karri
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 819-823, 2013
Leveraging memristive systems in the construction of digital logic circuits
GS Rose, J Rajendran, H Manem, R Karri, RE Pino
Proceedings of the IEEE 100 (6), 2033-2049, 2011
What to lock? Functional and parametric locking
M Yasin, A Sengupta, BC Schafer, Y Makris, O Sinanoglu, J Rajendran
Proceedings of the on Great Lakes Symposium on VLSI 2017, 351-356, 2017
Trustworthy hardware: Trojan detection and design-for-trust challenges
M Tehranipoor, H Salmani, X Zhang, M Wang, R Karri, J Rajendran, ...
Computer 44 (7), 66-74, 2010
Sneak-path testing of crossbar-based nonvolatile random access memories
S Kannan, J Rajendran, R Karri, O Sinanoglu
IEEE Transactions on Nanotechnology 12 (3), 413-426, 2013
Detecting malicious modifications of data in third-party intellectual property cores
J Rajendran, V Vedula, R Karri
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
Nano meets security: Exploring nanoelectronic devices for security applications
J Rajendran, R Karri, JB Wendt, M Potkonjak, N McDonald, GS Rose, ...
Proceedings of the IEEE 103 (5), 829-849, 2015
Nano-PPUF: A memristor-based security primitive
J Rajendran, GS Rose, R Karri, M Potkonjak
2012 IEEE Computer Society Annual Symposium on VLSI, 84-87, 2012
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