Leveraging memristive systems in the construction of digital logic circuits GS Rose, J Rajendran, H Manem, R Karri, RE Pino Proceedings of the IEEE 100 (6), 2033-2049, 2011 | 152 | 2011 |
Design considerations for variation tolerant multilevel CMOS/Nano memristor memory H Manem, GS Rose, X He, W Wang Proceedings of the 20th symposium on Great lakes symposium on VLSI, 287-292, 2010 | 115 | 2010 |
An energy-efficient memristive threshold logic circuit J Rajendran, H Manem, R Karri, GS Rose IEEE Transactions on Computers 61 (4), 474-487, 2012 | 114 | 2012 |
A read-monitored write circuit for 1T1M multi-level memristor memories H Manem, GS Rose 2011 IEEE international symposium of circuits and systems (ISCAS), 2938-2941, 2011 | 93 | 2011 |
Nanoscale hafnium oxide rram devices exhibit pulse dependent behavior and multi-level resistance capability K Beckmann, J Holt, H Manem, J Van Nostrand, NC Cady Mrs Advances 1 (49), 3355-3360, 2016 | 86 | 2016 |
Design considerations for multilevel CMOS/nano memristive memory H Manem, J Rajendran, GS Rose ACM Journal on Emerging Technologies in Computing Systems (JETC) 8 (1), 1-22, 2012 | 85 | 2012 |
Memristor based programmable threshold logic array J Rajendran, H Manem, R Karri, GS Rose 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 5-10, 2010 | 80 | 2010 |
An approach to tolerate process related variations in memristor-based applications J Rajendran, H Maenm, R Karri, GS Rose 2011 24th Internatioal Conference on VLSI Design, 18-23, 2011 | 49 | 2011 |
Stochastic gradient descent inspired training technique for a CMOS/nano memristive trainable threshold gate array H Manem, J Rajendran, GS Rose IEEE Transactions on Circuits and Systems I: Regular Papers 59 (5), 1051-1060, 2012 | 45 | 2012 |
Techniques for improved reliability in memristive crossbar PUF circuits M Uddin, MB Majumder, GS Rose, K Beckmann, H Manem, Z Alamgir, ... 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 212-217, 2016 | 43 | 2016 |
Performance enhancement of a time-delay PUF design by utilizing integrated nanoscale ReRAM devices K Beckmann, H Manem, NC Cady IEEE Transactions on Emerging Topics in Computing 5 (3), 304-316, 2016 | 37 | 2016 |
Design considerations for memristive crossbar physical unclonable functions M Uddin, MDB Majumder, K Beckmann, H Manem, Z Alamgir, NC Cady, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 14 (1), 1-23, 2017 | 29 | 2017 |
NDR based threshold logic fabric with memristive synapses J Rajendran, H Manem, GS Rose 2009 9th IEEE Conference on Nanotechnology (IEEE-NANO), 725-728, 2009 | 20 | 2009 |
An extendable multi-purpose 3D neuromorphic fabric using nanoscale memristors H Manem, K Beckmann, M Xu, R Carroll, R Geer, NC Cady 2015 IEEE Symposium on Computational Intelligence for Security and Defense …, 2015 | 14 | 2015 |
A hafnium-oxide memristive dynamic adaptive neural network array G Chakma, ME Dean, GS Rose, K Beckmann, H Manem, N Cady International Workshop on Post-Moore’s Era Supercomputing (PMES), Salt Lake …, 2016 | 12 | 2016 |
Inversion schemes for sublithographic programmable logic arrays B Gojman, H Manem, GS Rose, A DeHon IET computers & digital techniques 3 (6), 625-642, 2009 | 12 | 2009 |
Towards memristive dynamic adaptive neural network arrays N Cady, K Beckmann, H Manem, M Dean, G Rose, JV Nostrand Proceedings of the Government Microcircuit Applications and Critical …, 2016 | 10 | 2016 |
A Crosstalk Minimization technique for sublithographic programmable logic arrays H Manem, GS Rose 2009 9th IEEE Conference on Nanotechnology (IEEE-NANO), 218-221, 2009 | 6 | 2009 |
A hybrid cmos/nano fpga architecture built fromprogrammable majority logic arrays H Manem, PC Paliwoda, GS Rose Proceedings of the 18th ACM Great Lakes symposium on VLSI, 249-254, 2008 | 6 | 2008 |
RF Characterization of Through Silicon Vias Test Structures in a 3‐Tier Stacked Wafer M Xu, R Carroll, H Manem, R Geer 2014 25th Annual SEMI Advanced Semiconductor Manufacturing Conference, 73-78, 2014 | 5 | 2014 |