Garrett S. Rose
Cited by
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A survey of neuromorphic computing and neural networks in hardware
CD Schuman, TE Potok, RM Patton, JD Birdwell, ME Dean, GS Rose, ...
arXiv preprint arXiv:1705.06963, 2017
Fault analysis-based logic encryption
J Rajendran, H Zhang, C Zhang, GS Rose, Y Pino, O Sinanoglu, R Karri
IEEE Transactions on computers 64 (2), 410-424, 2013
Memristor crossbar-based neuromorphic computing system: A case study
M Hu, H Li, Y Chen, Q Wu, GS Rose, RW Linderman
IEEE transactions on neural networks and learning systems 25 (10), 1864-1878, 2014
Hardware realization of BSB recall function using memristor crossbar arrays
M Hu, H Li, Q Wu, GS Rose
Proceedings of the 49th annual design automation conference, 498-503, 2012
Leveraging memristive systems in the construction of digital logic circuits
GS Rose, J Rajendran, H Manem, R Karri, RE Pino
Proceedings of the IEEE 100 (6), 2033-2049, 2011
Memristive ion channel-doped biomembranes as synaptic mimics
JS Najem, GJ Taylor, RJ Weiss, MS Hasan, G Rose, CD Schuman, ...
ACS nano 12 (5), 4702-4711, 2018
A write-time based memristive PUF for hardware security applications
GS Rose, N McDonald, LK Yan, B Wysocki
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 830-833, 2013
Nano meets security: Exploring nanoelectronic devices for security applications
J Rajendran, R Karri, JB Wendt, M Potkonjak, N McDonald, GS Rose, ...
Proceedings of the IEEE 103 (5), 829-849, 2015
Nano-PPUF: A memristor-based security primitive
J Rajendran, GS Rose, R Karri, M Potkonjak
2012 IEEE Computer Society Annual Symposium on VLSI, 84-87, 2012
Design considerations for variation tolerant multilevel CMOS/Nano memristor memory
H Manem, GS Rose, X He, W Wang
Proceedings of the 20th symposium on Great lakes symposium on VLSI, 287-292, 2010
An energy-efficient memristive threshold logic circuit
J Rajendran, H Manem, R Karri, GS Rose
IEEE Transactions on Computers 61 (4), 474-487, 2012
A study of complex deep learning networks on high-performance, neuromorphic, and quantum computers
TE Potok, C Schuman, S Young, R Patton, F Spedalieri, J Liu, KT Yao, ...
ACM Journal on Emerging Technologies in Computing Systems (JETC) 14 (2), 1-21, 2018
A review of spiking neuromorphic hardware communication systems
AR Young, ME Dean, JS Plank, GS Rose
IEEE Access 7, 135606-135620, 2019
A read-monitored write circuit for 1T1M multi-level memristor memories
H Manem, GS Rose
2011 IEEE international symposium of circuits and systems (ISCAS), 2938-2941, 2011
Apparatus for performing matrix vector multiplication approximation using crossbar arrays of resistive memory devices
R Linderman, Q Wu, G Rose, H Li, Y Chen, M Hu
US Patent 9,152,827, 2015
Design considerations for multilevel CMOS/nano memristive memory
H Manem, J Rajendran, GS Rose
ACM Journal on Emerging Technologies in Computing Systems (JETC) 8 (1), 1-22, 2012
Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems
Q Wu, R Linderman, G Rose, H Li, Y Chen, M Hu
US Patent 9,715,655, 2017
Foundations of memristor based PUF architectures
GS Rose, N McDonald, LK Yan, B Wysocki, K Xu
2013 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2013
Memristor based programmable threshold logic array
J Rajendran, H Manem, R Karri, GS Rose
2010 IEEE/ACM International Symposium on Nanoscale Architectures, 5-10, 2010
BSB training scheme implementation on memristor-based circuit
M Hu, H Li, Y Chen, Q Wu, GS Rose
2013 IEEE symposium on computational intelligence for security and defense …, 2013
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