| A comprehensive survey on model quantization for deep neural networks in image classification B Rokh, A Azarpeyvand, A Khanteymoori ACM Transactions on Intelligent Systems and Technology 14 (6), 1-50, 2023 | 84* | 2023 |
| Code acceleration using memristor-based approximate matrix multiplier: Application to convolutional neural networks M Nourazar, V Rashtchi, A Azarpeyvand, F Merrikh-Bayat IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018 | 29 | 2018 |
| Instruction reliability analysis for embedded processors A Azarpeyvand, ME Salehi, F Firouzi, A Yazdanbakhsh, SM Fakhraie 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and …, 2010 | 23 | 2010 |
| Reduced-memory direct digital frequency synthesizer using parabolic initial guess AM Sodagar, GR Lahiji, A Azarpeyvand Analog Integrated Circuits and Signal Processing 34, 89-96, 2003 | 18 | 2003 |
| Propounding first artificial intelligence approach for predicting robbery behavior potential in an indoor security camera S Pouyan, M Charmi, A Azarpeyvand, H Hassanpoor IEEE Access 11, 60471-60489, 2023 | 13 | 2023 |
| Adaptive fault-tolerant DVFS with dynamic online AVF prediction F Firouzi, A Azarpeyvand, ME Salehi, SM Fakhraie Microelectronics Reliability 52 (6), 1197-1208, 2012 | 12 | 2012 |
| Fast and accurate architectural vulnerability analysis for embedded processors using instruction vulnerability factor A Azarpeyvand, ME Salehi, SM Fakhraie, S Safari Microprocessors and Microsystems 42, 113-126, 2016 | 10 | 2016 |
| AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators M Taheri, N Cherezova, S Nazari, A Rafiq, A Azarpeyvand, ... 2024 IEEE European Test Symposium (ETS), 1-4, 2024 | 9 | 2024 |
| Towards memristor-based approximate accelerator: Application to complex-valued FIR filter bank M Nourazar, V Rashtchi, F Merrikh-Bayat, A Azarpeyvand Analog Integrated Circuits and Signal Processing 96 (3), 577-588, 2018 | 9 | 2018 |
| Memristor-based approximate matrix multiplier M Nourazar, V Rashtchi, A Azarpeyvand, F Merrikh-Bayat Analog Integrated Circuits and Signal Processing 93 (2), 363-373, 2017 | 9 | 2017 |
| Data-driven and knowledge-based algorithms for gene network reconstruction on high-dimensional data O Abbaszadeh, A Azarpeyvand, A Khanteymoori, A Bahari IEEE/ACM Transactions on Computational Biology and Bioinformatics 19 (3 …, 2020 | 8 | 2020 |
| Vulnerability analysis for custom instructions A Azarpeyvand, ME Salehi, SM Fakhraie 2012 15th Euromicro Conference on Digital System Design, 144-147, 2012 | 8 | 2012 |
| CIVA: Custom instruction vulnerability analysis framework A Azarpeyvand, ME Salehi, SM Fakhraie 2012 IEEE 15th International Symposium on Design and Diagnostics of …, 2012 | 8 | 2012 |
| Reliability considerations in dynamic voltage and frequency scaling schemes F Firouzi, ME Salehi, A Azarpeyvand, SM Fakhraie, F Wang 5th International Conference on Design & Technology of Integrated Systems in …, 2010 | 7 | 2010 |
| Energy/throughput trade-off in a fully asynchronous NoC for GALS-based MPSoC architectures A Rahimi, ME Salehi, S Mohammadi, SM Fakhraie, A Azarpeyvand 5th International Conference on Design & Technology of Integrated Systems in …, 2010 | 7 | 2010 |
| Reliability aware throughput management of chip multi-processor architecture via thread migration F Pouyan, A Azarpeyvand, S Safari, SM Fakhraie The Journal of Supercomputing 72, 1363-1380, 2016 | 6 | 2016 |
| Parallel algorithms for inferring gene regulatory networks: a review O Abbaszadeh, AR Khanteymoori, A Azarpeyvand Current genomics 19 (7), 603-614, 2018 | 5 | 2018 |
| A novel architecture for sine-output direct digital frequency synthesizers using parabolic approximation AM Sodagar, GR Lahiji, A Azarpeyvand ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and …, 2000 | 5 | 2000 |
| Parallel chaos-based image encryption algorithm: high-level synthesis and FPGA implementation SS Moghimi Moghaddam, V Rashtchi, A Azarpeyvand The Journal of Supercomputing 80 (8), 10985-11013, 2024 | 4* | 2024 |
| Vulnerability analysis of adder architectures considering design and synthesis constraints M Salehi, A Azarpeyvand, AH Aboutalebi Journal of Electronic Testing 34, 7-14, 2018 | 4 | 2018 |
Vahid RashtchiUniversity of ZanjanVerified email at znu.ac.ir
