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| High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors P Packan, S Akbar, M Armstrong, D Bergstrom, M Brazier, H Deshpande, ... 2009 IEEE international electron devices meeting (IEDM), 1-4, 2009 | 288 | 2009 |
| A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array S Natarajan, M Armstrong, M Bost, R Brain, M Brazier, CH Chang, ... 2008 IEEE International Electron Devices Meeting, 1-3, 2008 | 286 | 2008 |
| Self-heat reliability considerations on Intel's 22nm Tri-Gate technology C Prasad, L Jiang, D Singh, M Agostinelli, C Auth, P Bai, T Eiles, J Hicks, ... 2013 IEEE International Reliability Physics Symposium (IRPS), 5D. 1.1-5D. 1.5, 2013 | 118 | 2013 |
| An advanced low power, high performance, strained channel 65nm technology S Tyagi, C Auth, P Bai, G Curello, H Deshpande, S Gannavaram, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 107 | 2005 |
| Intel 22nm FinFET (22FFL) process technology for RF and mm wave applications and circuit design optimization for FinFET technology HJ Lee, S Rami, S Ravikumar, V Neeli, K Phoa, B Sell, Y Zhang 2018 IEEE International Electron Devices Meeting (IEDM), 14.1. 1-14.1. 4, 2018 | 106 | 2018 |
| 2 MB array-level demonstration of STT-MRAM process and performance towards L4 cache applications JG Alzate, U Arslan, P Bai, J Brockman, YJ Chen, N Das, K Fischer, ... 2019 IEEE International Electron Devices Meeting (IEDM), 2.4. 1-2.4. 4, 2019 | 102 | 2019 |
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| Charge-based capacitance measurements (CBCM) on MOS devices B Sell, A Avellán, WH Krautschneider IEEE transactions on device and materials reliability 2 (1), 9-12, 2002 | 34 | 2002 |
| Chemical vapor deposition of tungsten silicide (WSix) for high aspect ratio applications B Sell, A Sänger, G Schulze-Icking, K Pomplun, W Krautschneider Thin Solid Films 443 (1-2), 97-107, 2003 | 28 | 2003 |
| Short channel effect of MOS devices by retrograde well engineering using tilted dopant implantation into recessed source/drain regions T Hoffmann, S Tyagi, G Curello, B Sell, C Auth US Patent App. 10/954,914, 2006 | 26 | 2006 |
| Integration of capacitor for sub-100-nm DRAM trench technology J Lutzen, A Birner, M Goldbach, M Gutsche, T Hecht, S Jakschik, A Orth, ... 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No …, 2002 | 25 | 2002 |
| Implementation of high power RF devices with hybrid workfunction and OxideThickness in 22nm low-power FinFET technology HJ Lee, S Morarka, S Rami, Q Yu, M Weiss, G Liu, M Armstrong, CY Su, ... 2019 IEEE International Electron Devices Meeting (IEDM), 25.4. 1-25.4. 4, 2019 | 22 | 2019 |
| Intel 4 CMOS technology featuring advanced FinFET transistors optimized for high density and high-performance computing B Sell, S An, J Armstrong, D Bahr, B Bains, R Bambery, K Bang, D Basu, ... 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022 | 19 | 2022 |
| IEDM Tech. Dig. P Packan, S Akbar, M Armstrong, D Bergstrom, M Brazier, H Deshpande IEDM Tech. Dig, 959-662, 2009 | 18 | 2009 |
| A 32-A, 5-V-input, 94.2% peak efficiency high-frequency power converter module featuring package-integrated low-voltage GaN nMOS power transistors N Desai, HW Then, J Yu, HK Krishnamurthy, WJ Lambert, N Butzen, ... IEEE Journal of Solid-State Circuits 57 (4), 1090-1099, 2022 | 15 | 2022 |
| Transistor reliability characterization and modeling of the 22FFL FinFET technology CY Su, M Armstrong, L Jiang, SA Kumar, CD Landon, S Liu, I Meric, ... 2018 IEEE International Reliability Physics Symposium (IRPS), 6F. 8-1-6F. 8-7, 2018 | 11 | 2018 |
| mmWave and sub-THz technology development in Intel 22nm FinFET (22FFL) process Q Yu, S Rami, J Waldemer, Y Ma, V Neeli, J Garrett, G Liu, J Koo, ... 2020 IEEE International Electron Devices Meeting (IEDM), 17.4. 1-17.4. 4, 2020 | 9 | 2020 |
