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Srinivasa Shashank Nuthakki
Srinivasa Shashank Nuthakki
Verified email at stanford.edu
Title
Cited by
Cited by
Year
Improved test pattern generation for hardware trojan detection using genetic algorithm and boolean satisfiability
S Saha, RS Chakraborty, SS Nuthakki, Anshul, D Mukhopadhyay
Cryptographic Hardware and Embedded Systems--CHES 2015: 17th International …, 2015
1242015
Anshul, and D. Mukhopadhyay. Improved test pattern generation for hardware trojan detection using genetic algorithm and boolean satisfiability
S Saha, RS Chakraborty, SS Nuthakki
International Workshop on Cryptographic Hardware and Embedded Systems (CHES …, 2015
452015
Symbolic quick error detection using symbolic initial state for pre-silicon verification
MR Fadiheh, J Urdahl, SS Nuthakki, S Mitra, C Barrett, D Stoffel, W Kunz
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 55-60, 2018
242018
Optimization of the IEEE 1687 access network for hybrid access schedules
SS Nuthakki, R Karmakar, S Chattopadhyay, K Chakrabarty
2016 IEEE 34th VLSI Test Symposium (VTS), 1-6, 2016
162016
Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED
F Lonsing, K Ganesan, M Mann, SS Nuthakki, E Singh, M Srouji, Y Yang, ...
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
82019
Effective pre-silicon verification of processor cores by breaking the bounds of symbolic quick error detection
K Ganesan, F Lonsing, SS Nuthakki, E Singh, MR Fadiheh, W Kunz, ...
arXiv preprint arXiv:2106.10392, 2021
42021
Integrated circuit chip with cores asymmetrically oriented with respect to each other
JS Nayyar, SS Nuthakki, R Gulati, A Shrimali
US Patent 10,002,056, 2018
42018
Integrated Circuit Chip with Cores Asymmetrically Oriented With Respect To Each Other
JS Nayyar, SS Nuthakki, R Gulati, A Shrimali
US Patent App. 18/323,931, 2023
12023
Integrated circuit chip with cores asymmetrically oriented with respect to each other
JS Nayyar, SS Nuthakki, R Gulati, A Shrimali
US Patent 11,698,841, 2023
12023
Integrated circuit chip with cores asymmetrically oriented with respect to each other
JS Nayyar, SS Nuthakki, R Gulati, A Shrimali
US Patent 10,649,865, 2020
12020
Test set customization for improved fault diagnosis without sacrificing coverage
SS Nuthakki, S Chattopadhyay, M Chakraborty
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 1574-1577, 2015
12015
Integrated circuit chip with cores asymmetrically oriented with respect to each other
JS Nayyar, SS Nuthakki, R Gulati, A Shrimali
US Patent 11,269,742, 2022
2022
Boosting the Bounds of Symbolic QED for Effective Pre-Silicon Verification of Processor Cores
K Ganesan, SS Nuthakki
arXiv preprint arXiv:1908.06757, 2019
2019
Integrated circuit chip with cores asymmetrically oriented with respect to each other
AS Jasbir Singh Nayyar, Shashank Srinivasa Nuthakki, Rahul Gulati
US Patent US10002056B2, 2018
2018
Integrated circuit chip with cores asymmetrically oriented with respect to each other
JS Nayyar, SS Nuthakki, R Gulati, A Shrimali
US Patent 10,002,056, 2018
2018
An Integrated Approach for Improving Compression and Diagnostic Properties of Test Sets
SS Nuthakki, S Chattopadhyay
2015 IEEE 24th Asian Test Symposium (ATS), 151-156, 2015
2015
Tutorial T2E: Pre-Silicon Verification and Post-Silicon Validation: Dramatic Improvements through Disruptive Innovations
S Mitra, SS Nuthakki, E Singh
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