| Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM MT Chang, P Rosenfeld, SL Lu, B Jacob 2013 IEEE 19th international symposium on high performance computer …, 2013 | 301 | 2013 |
| DRAM refresh mechanisms, penalties, and trade-offs IS Bhati, MT Chang, Z Chishti, SL Lu, B Jacob IEEE Transactions on Computers 65 (1), 108-121, 2016 | 167 | 2016 |
| 3-D stacked memory with reconfigurable compute logic MT Chang, P Gera, D Niu, H Zheng US Patent 11,079,936, 2021 | 35 | 2021 |
| Coordinated in-module RAS features for synchronous DDR compatible memory MT Chang, D Niu, H Zheng, SY Lim, KIM Indong, J Choi US Patent 10,592,114, 2020 | 30 | 2020 |
| An Integrated Simulation Infrastructure for the Entire Memory Hierarchy: Cache, DRAM, Nonvolatile Memory, and Disk J Stevens, P Tschirhart, MT Chang, I Bhati, P Enns, J Greensky, Z Chisti, ... Intel® Technology Journal 17 (1), 2013 | 28 | 2013 |
| Optimized hopscotch multiple hash tables for efficient memory in-line deduplication application F Sala, C Hu, H Zheng, D Niu, MT Chang US Patent 9,983,821, 2018 | 19 | 2018 |
| A 65nm low power 2T1D embedded DRAM with leakage current reduction MT Chang, PT Huang, W Hwang 2007 IEEE International SOC Conference, 207-210, 2007 | 18 | 2007 |
| Asynchronous communication protocol compatible with synchronous DDR protocol D Niu, MT Chang, H Zheng, SY Lim, KIM Indong, J Choi, C Hanson US Patent 10,621,119, 2020 | 17 | 2020 |
| ISA extension for high-bandwidth memory MT Chang, KT Malladi, D Niu, H Zheng US Patent 10,866,900, 2020 | 15 | 2020 |
| A fully-differential subthreshold SRAM cell with auto-compensation MT Chang, W Hwang APCCAS 2008-2008 IEEE Asia Pacific Conference on Circuits and Systems, 1771-1774, 2008 | 15 | 2008 |
| System architecture with memory channel DRAM FPGA module H Zheng, MT Chang US Patent 10,013,212, 2018 | 14 | 2018 |
| HBM with in-memory cache manager T Stocksdale, MT Chang, H Zheng US Patent 10,180,906, 2019 | 13 | 2019 |
| Hybrid memory module and transaction-based memory interface D Niu, MT Chang, H Zheng US Patent 9,971,511, 2018 | 13 | 2018 |
| Transaction-based hybrid memory module MT Chang, H Zheng, D Niu US Patent App. 14/947,145, 2017 | 13 | 2017 |
| Multi-cell structure for non-volatile resistive memory D Niu, MT Chang, H Zheng US Patent 10,929,026, 2021 | 12 | 2021 |
| Coordinated near-far memory controller for process-in-HBM MT Chang, D Niu, H Zheng US Patent 10,437,482, 2019 | 12 | 2019 |
| Self-optimized power management for DDR-compatible memory systems MT Chang, D Niu, H Zheng, C Hanson, SY Lim, KIM Indong, J Choi US Patent 10,347,306, 2019 | 12 | 2019 |
| A robust ultra-low power asynchronous FIFO memory with self-adaptive power control MT Chang, PT Huang, W Hwang 2008 IEEE International SOC Conference, 175-178, 2008 | 12 | 2008 |
| Systems and methods for write and flush support in hybrid memory MT Chang, D Niu, H Zheng, H Nam, Y Cho, SY Lim US Patent 11,175,853, 2021 | 10 | 2021 |
| Techniques to reduce read-modify-write overhead in hybrid DRAM/NAND memory MT Chang, H Nam, Y Kim, Y Cho, D Niu, H Zheng US Patent 10,762,000, 2020 | 10 | 2020 |
Shih-Lien Lu (Linus)Washington State UniversityVerified email at wsu.edu
