| Flowblaze: Stateful packet processing in hardware S Pontarelli, R Bifulco, M Bonola, C Cascone, M Spaziani, V Bruschi, ... Proceedings of the 16th USENIX Symposium on Networked Systems Design and …, 2019 | 139 | 2019 |
| A new hardware/software platform and a new 1/E neutron source for soft error studies: Testing FPGAs at the ISIS facility M Violante, L Sterpone, A Manuzzato, S Gerardin, P Rech, M Bagatin, ... Nuclear Science, IEEE Transactions on 54 (4), 1184-1189, 2007 | 106 | 2007 |
| Survey of performance acceleration techniques for network function virtualization L Linguaglossa, S Lange, S Pontarelli, G Rétvári, D Rossi, T Zinner, ... Proceedings of the IEEE 107 (4), 746-764, 2019 | 98 | 2019 |
| Totally fault tolerant RNS based FIR filters S Pontarelli, GC Cardarilli, M Re, A Salsano 2008 14th IEEE International On-Line Testing Symposium, 192-194, 2008 | 91 | 2008 |
| Design of a fault tolerant solid state mass memory GC Cardarilli, A Leandri, P Marinucci, M Ottavi, S Pontarelli, M Re, ... IEEE Transactions on Reliability 52 (4), 476-491, 2003 | 87 | 2003 |
| Traffic-aware design of a high-speed FPGA network intrusion detection system S Pontarelli, G Bianchi, S Teofili IEEE Transactions on Computers 62 (11), 2322-2334, 2012 | 86 | 2012 |
| High-speed software data plane via vectorized packet processing D Barach, L Linguaglossa, D Marion, P Pfister, S Pontarelli, D Rossi IEEE Communications Magazine 56 (12), 97-103, 2018 | 77* | 2018 |
| Adaptive cuckoo filters M Mitzenmacher, S Pontarelli, P Reviriego Journal of Experimental Algorithmics (JEA) 25, 1-20, 2020 | 71 | 2020 |
| QCA circuits for robust coplanar crossing S Bhanja, M Ottavi, F Lombardi, S Pontarelli Journal of Electronic Testing 23 (2), 193-210, 2007 | 71 | 2007 |
| Fault tolerant solid state mass memory for space applications GC Cardarilli, M Ottavi, S Pontarelli, M Re, A Salsano IEEE Transactions on Aerospace and Electronic Systems 41 (4), 1353-1372, 2005 | 70 | 2005 |
| MCU tolerance in SRAMs through low-redundancy triple adjacent error correction LJ Saiz-Adalid, P Reviriego, P Gil, S Pontarelli, JA Maestro IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (10 …, 2014 | 64 | 2014 |
| hXDP: Efficient Software Packet Processing on FPGA NICs. MS Brunella, G Belocchi, M Bonola, S Pontarelli, G Siracusano, G Bianchi, ... OSDI 20, 973-990, 2020 | 58 | 2020 |
| Tuplemerge: Fast software packet processing for online packet classification J Daly, V Bruschi, L Linguaglossa, S Pontarelli, D Rossi, J Tollet, E Torng, ... IEEE/ACM transactions on networking 27 (4), 1417-1431, 2019 | 56 | 2019 |
| Open Packet Processor: a programmable architecture for wire speed platform-independent stateful in-network processing G Bianchi, M Bonola, S Pontarelli, D Sanvito, A Capone, C Cascone arXiv preprint arXiv:1605.01977, 2016 | 55 | 2016 |
| A method to construct low delay single error correction codes for protecting data bits only P Reviriego, S Pontarelli, JA Maestro, M Ottavi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 54 | 2013 |
| Bit flip injection in processor-based architectures: a case study GC Cardarilli, F Kaddour, A Leandri, M Ottavi, S Pontarelli, R Velazco Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW …, 2002 | 53 | 2002 |
| Complementary resistive switch-based arithmetic logic implementations using material implication Y Yang, J Mathew, S Pontarelli, M Ottavi, DK Pradhan IEEE Transactions on nanotechnology 15 (1), 94-108, 2015 | 51 | 2015 |
| Area efficient concurrent error detection and correction for parallel filters P Reviriego, S Pontarelli, CJ Bleakley, JA Maestro Electronics letters 48 (20), 1258-1260, 2012 | 51 | 2012 |
| Partially reversible pipelined QCA circuits: combining low power with high throughput M Ottavi, S Pontarelli, EP DeBenedictis, A Salsano, S Frost-Murphy, ... IEEE transactions on nanotechnology 10 (6), 1383-1393, 2011 | 43 | 2011 |
| Concurrent error detection in Reed–Solomon encoders and decoders GC Cardarilli, S Pontarelli, M Re, A Salsano IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (7), 842-846, 2007 | 41 | 2007 |
Pedro ReviriegoUniversidad Politécnica de MadridVerified email at upm.es
