| Method and apparatus for dynamic load balancing over a network link bundle S Hilla, KH Potter, J Marshall US Patent 7,623,455, 2009 | 151 | 2009 |
| High speed parallel/serial link for data communication R Gerowitz, Gray, Marshall, Riedle US Patent 6,222,380, 2001 | 109* | 2001 |
| Sequence control mechanism for enabling out of order context processing D Kerr, JB Scott, JW Marshall, KH Potter, S Nellenbach US Patent 6,804,815, 2004 | 66 | 2004 |
| Packet striping across a parallel header processor D Kerr, J Scott, JW Marshall, S Nellenbach US Patent 6,965,615, 2005 | 58 | 2005 |
| Group and virtual locking mechanism for inter processor synchronization JW Marshall, KH Potter US Patent 6,529,983, 2003 | 57 | 2003 |
| Barrier synchronization mechanism for processors of a systolic array JW Marshall, BS Burns, D Kerr US Patent 7,100,021, 2006 | 52 | 2006 |
| Programmable packet classification system using an array of uniform content-addressable memories JW Marshall, RE Schroter, H Levenson US Patent 8,040,886, 2011 | 47 | 2011 |
| Full access to memory interfaces via remote request RE Jeter Jr, JW Marshall, JB Scott US Patent 7,290,096, 2007 | 47 | 2007 |
| Multi-threaded processing using path locks R Jeter, T Garner, J Marshall, A Kirk US Patent 8,010,966, 2011 | 39 | 2011 |
| Processor isolation method for integrated multi-processor systems W Fredenburg, KM Key, ML Wright, JW Marshall US Patent 6,681,341, 2004 | 34 | 2004 |
| Full access to memory interfaces via remote request RE Jeter Jr, JW Marshall, JB Scott US Patent 7,047,370, 2006 | 32 | 2006 |
| Initialization system for recovering bits and group of bits from a communications channel R Buchanan, JW Marshall US Patent 6,611,217, 2003 | 32 | 2003 |
| Attribute based memory pre-fetching technique JW Marshall US Patent 6,728,839, 2004 | 31 | 2004 |
| Group and virtual locking mechanism for inter processor synchronization JW Marshall, KH Potter US Patent 6,662,252, 2003 | 31 | 2003 |
| System and method for modifying data transferred from a source to a destination JW Marshall, VK Parameshwara, JB Scott US Patent 7,937,495, 2011 | 28 | 2011 |
| Zero overhead resource locks with attributes RE Jeter Jr, KH Potter, D Kerr, JW Marshall, M Changela US Patent 7,290,105, 2007 | 28 | 2007 |
| Tightly coupled software protocol decode with hardware data encryption D Kerr, JW Marshall US Patent 6,920,562, 2005 | 24 | 2005 |
| Selected register decode values for pipeline stage register addressing D Kerr, JW Marshall US Patent 7,139,899, 2006 | 22 | 2006 |
| Pvpp: A programmable vector packet processor S Choi, X Long, M Shahbaz, S Booth, A Keep, J Marshall, C Kim Proceedings of the Symposium on SDN Research, 197-198, 2017 | 20 | 2017 |
| Inter-chip processor control plane communication R Schroter, JW Marshall, KH Potter US Patent 7,447,872, 2008 | 20 | 2008 |
Minseok KwonProfessor of Computer Science, Rochester Institute of TechnologyVerified email at cs.rit.edu
