Marco Spaziani Brunella
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FlowBlaze: Stateful Packet Processing in Hardware
S Pontarelli, R Bifulco, M Bonola, C Cascone, M Spaziani Brunella, ...
16th USENIX Symposium on Networked Systems Design and Implementation (NSDI …, 2019
hXDP: Efficient software packet processing on FPGA NICs
M Spaziani Brunella, G Belocchi, M Bonola, S Pontarelli, G Siracusano, ...
Communications of the ACM 65 (8), 92-100, 2022
hXDP: Efficient Software Packet Processing on FPGA NICs
M Spaziani Brunella, G Belocchi, M Bonola, S Pontarelli, G Siracusano, ...
14th USENIX Symposium on Operating Systems Design and Implementation (OSDI …, 2020
Faster Software Packet Processing on FPGA NICs with eBPF Program Warping
M Bonola, G Belocchi, A Tulumello, M Spaziani Brunella, G Siracusano, ...
2022 USENIX Annual Technical Conference (USENIX ATC 22), 987-1004, 2022
Foreshadow-VMM: Feasibility and network perspective
MS Brunella, G Bianchi, S Turco, F Quaglia, N Blefari-Melazzi
2019 IEEE Conference on Network Softwarization (NetSoft), 257-259, 2019
V-PMP: A VLIW Packet Manipulator Processor
MS Brunella, S Pontarelli, M Bonola, G Bianchi
2018 European Conference on Networks and Communications (EuCNC), 1-9, 2018
Hyperion: A Case for Unified, Self-Hosting, Zero-CPU Data-Processing Units (DPUs)
M Spaziani Brunella, M Bonola, A Trivedi
arXiv e-prints, arXiv: 2205.08882, 2022
Robust throughput boosting for low latency dynamic partial reconfiguration
A Nannarelli, M Re, GC Cardarilli, L Di Nunzio, MS Brunella, R Fazzolari, ...
2017 30th IEEE International System-on-Chip Conference (SOCC), 86-90, 2017
CPU-free Computing: A Vision with a Blueprint
A Trivedi, MS Brunella
Proceedings of the 19th Workshop on Hot Topics in Operating Systems, 1-14, 2023
Foreshadow-VMM: on the practical feasibility of L1 cache Terminal Fault attacks
MS Brunella, S Turco, G Bianchi, NB Melazzi
ITASEC 2019, 2019
Packet Manipulator Processor: A RISC-V VLIW core for networking applications
MS Brunella, S Pontarelli, F Marrese, M Bonola, G Bianchi
7th RISC-V Workshop, 2017
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