Marco Spaziani Brunella

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marco bonolaconsorzio nazionale interuniversitario per le telecomunicazioniVerified email at uniroma2.it
giuseppe bianchiUniversità di Roma Tor VergataVerified email at uniroma2.it
Salvatore PontarelliComputer Science - SapienzaVerified email at uniroma1.it
Roberto BifulcoNEC Laboratories EuropeVerified email at neclab.eu
Giuseppe SiracusanoNEC Laboratories EuropeVerified email at neclab.eu
Michio HondaLecturer (Assistant Professor) in Networked Systems, University of EdinburghVerified email at ed.ac.uk
Valerio BruschiPhD, Università di Roma Tor Vergata/CNITVerified email at uniroma2.it
Davide SanvitoNEC Laboratories EuropeVerified email at neclab.eu
Carmelo CasconeIntelVerified email at intel.com
Antonio CaponeProfessor - Politecnico di MilanoVerified email at polimi.it
Felipe HuiciNEC Laboratories EuropeVerified email at neclab.eu
Nicola Blefari MelazziProfessor of Telecommunications, University of Rome, Tor VergataVerified email at uniroma2.it
Francesco QuagliaUniversita' di Roma Tor VergataVerified email at uniroma2.it

Marco Spaziani Brunella

PhD Candidate, University of Rome Tor Vergata and University of California Berkeley

Verified email at berkeley.edu - Homepage

Computer Architecture Domain Specific Accelerators Reconfigurable Computing


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FlowBlaze: Stateful Packet Processing in Hardware S Pontarelli, R Bifulco, M Bonola, C Cascone, M Spaziani Brunella, ... 16th USENIX Symposium on Networked Systems Design and Implementation (NSDI …, 2019	139	2019
hXDP: Efficient software packet processing on FPGA NICs M Spaziani Brunella, G Belocchi, M Bonola, S Pontarelli, G Siracusano, ... Communications of the ACM 65 (8), 92-100, 2022	54*	2022
V-PMP: A VLIW Packet Manipulator Processor MS Brunella, S Pontarelli, M Bonola, G Bianchi 2018 European Conference on Networks and Communications (EuCNC), 1-9, 2018	7	2018
The magazine archive includes every article published in Communications of the ACM for over the past 50 years. MS Brunella, G Belocchi, M Bonola, S Pontarelli, G Siracusano, G Bianchi, ... Communications of the ACM 65 (8), 92-100, 2022	6	2022
hXDP: Efficient Software Packet Processing on FPGA NICs M Spaziani Brunella, G Belocchi, M Bonola, S Pontarelli, G Siracusano, ... 14th USENIX Symposium on Operating Systems Design and Implementation (OSDI …, 2020	5	2020
Foreshadow-vmm: Feasibility and network perspective MS Brunella, G Bianchi, S Turco, F Quaglia, N Blefari-Melazzi 2019 IEEE Conference on Network Softwarization (NetSoft), 257-259, 2019	3	2019
Robust throughput boosting for low latency dynamic partial reconfiguration A Nannarelli, M Re, GC Cardarilli, L Di Nunzio, MS Brunella, R Fazzolari, ... 2017 30th IEEE International System-on-Chip Conference (SOCC), 86-90, 2017	2	2017
Hyperion: A Case for Unified, Self-Hosting, Zero-CPU Data-Processing Units (DPUs) M Spaziani Brunella, M Bonola, A Trivedi arXiv e-prints, arXiv: 2205.08882, 2022	1*	2022
Foreshadow-VMM: on the practical feasibility of L1 cache Terminal Fault attacks MS Brunella, S Turco, G Bianchi, NB Melazzi ITASEC 2019, 2019	1	2019
Packet Manipulator Processor: A RISC-V VLIW core for networking applications MS Brunella, S Pontarelli, F Marrese, M Bonola, G Bianchi 7th RISC-V Workshop, 2017	1*	2017
Faster Software Packet Processing on FPGA NICs with eBPF Program Warping M Bonola, G Belocchi, A Tulumello, M Spaziani Brunella, G Siracusano, ... 2022 USENIX Annual Technical Conference (USENIX ATC 22), 987-1004, 2022		2022

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