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Vivekananda Vedula
Vivekananda Vedula
Freescale Semiconductor
Verified email at arm.com
Title
Cited by
Cited by
Year
Detecting malicious modifications of data in third-party intellectual property cores
J Rajendran, V Vedula, R Karri
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
1382015
Formal security verification of third party intellectual property cores for information leakage
J Rajendran, AM Dhandayuthapany, V Vedula, R Karri
2016 29th International conference on VLSI design and 2016 15th …, 2016
792016
FACTOR: A hierarchical methodology for functional test generation and testability analysis
VM Vedula, JA Abraham
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
432002
Verifying properties using sequential ATPG [IC design]
JA Abraham, VM Vedula
Proceedings. International Test Conference, 194-202, 2002
412002
Native mode functional self-test generation for systems-on-chip
K Jayaraman, VM Vedula, JA Abraham
Proceedings International Symposium on Quality Electronic Design, 280-285, 2002
392002
A hierarchical test generation approach using program slicing techniques on hardware description languages
VM Vedula, JA Abraham, J Bhadra, R Tupuri
Journal of Electronic Testing 19, 149-160, 2003
372003
Power virus generation using behavioral models of circuits
K Najeeb, V Vardhan, R Konda, S Kumar, S Hari, V Kamakoti, VM Vedula
25th IEEE VLSI Test Symposium (VTS'07), 35-42, 2007
302007
Program slicing for hierarchical test generation
VM Vedula, JA Abraham, J Bhadra
Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), 237-243, 2002
292002
Formal verification using bounded model checking: SAT versus sequential ATPG engines
DG Saab, JA Abraham, VM Vedula
16th International Conference on VLSI Design, 2003. Proceedings., 243-248, 2003
282003
Automatic constraint based test generation for behavioral HDL models
SKS Hari, VVR Konda, V Kamakoti, VM Vedula, KS Maneperambil
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (4), 408-421, 2008
202008
Program slicing for ATPG-based property checking
VM Vedula, WJ Townsend, JA Abraham
17th International Conference on VLSI Design. Proceedings., 591-596, 2004
202004
A novel methodology for hierarchical test generation using functional constraint composition
VM Vedula, JA Abraham
Proceedings IEEE International High-Level Design Validation and Test …, 2000
172000
System, method and computer-accessible medium for security verification of third party intellectual property cores
V Vedula, J Rajendran, A Dhandayuthapany, R Karri
US Patent 10,083,303, 2018
162018
System, method and computer-accessible medium for security verification of third party intellectual property cores
V Vedula, J Rajendran, A Dhandayuthapany, R Karri
US Patent App. 14/874,794, 2016
102016
Controllability-driven power virus generation for digital circuits
K Najeeb, K Gururaj, V Kamakoti, VM Vedula
20th International Conference on VLSI Design held jointly with 6th …, 2007
102007
Circuit modeling apparatus, systems, and methods
J Abraham, V Vedula
US Patent App. 11/017,378, 2005
92005
A scalable symbolic simulator for Verilog RTL
S Sunkari, S Chakraborty, V Vedula, K Maneparambil
2007 Eighth International Workshop on Microprocessor Test and Verification …, 2007
82007
A unified formal framework for analyzing functional and speed-path properties
O Olivo, S Ray, J Bhadra, V Vedula
2011 12th International Workshop on Microprocessor Test and Verification, 44-45, 2011
32011
A novel unified framework for functional verification of processors using constraint solvers
D Prasad, R Archana, V Karthik, VK Senthilkumar, SM Kailasnath, ...
Proc. VLSI Des. Test Symp.(VDAT), 418-426, 2006
32006
Security verification of 3rd party intellectual property cores for information leakage
V Vedula, J Rajendran, A Murugadhandayuthapany, R Karri
Proceedings of the GOMACTECH, 2015
22015
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