| Pseudorandom construction of low-density parity-check codes using linear congruential sequences A Prabhakar, K Narayanan IEEE Transactions on Communications 50 (9), 1389-1396, 2002 | 67 | 2002 |
| A massively scaleable decoder architecture for low-density parity-check codes A Selvarathinam, G Choi, K Narayanan, A Prabhakar, E Kim 2003 IEEE International Symposium on Circuits and Systems (ISCAS) 2, II-II, 2003 | 49 | 2003 |
| Ldpc decoder with an improved llr update method using a set of relative values free from a shifting action Y Zhong, A Prabhakar US Patent App. 11/853,093, 2009 | 29 | 2009 |
| A memory efficient serial LDPC decoder architecture A Prabhakar, K Narayanan Proceedings.(ICASSP'05). IEEE International Conference on Acoustics, Speech …, 2005 | 29 | 2005 |
| receiver architecture having a ldpc decoder with an improved llr update method for memory reduction Y Zhong, A Prabhakar, D Venkatachalam US Patent App. 11/557,491, 2008 | 20 | 2008 |
| Techniques for adaptive LDPC decoding J Yen, A Prabhakar, CL Wang US Patent 9,866,241, 2018 | 19 | 2018 |
| Memory efficient scalable decoder architectures for low density parity check codes A Prabhakar, K Narayanan Wireless Communication Laboratory Tech Report, Texas A&M, 2006 | 12 | 2006 |
| Method and apparatus for decoding a ldpc code A Prabhakar, Z Yan US Patent App. 11/767,466, 2008 | 10 | 2008 |
| Memory system with hybrid decoding scheme and method of operating such memory system N Kumar, A Bhatia, A Prabhakar, C Xiong, F Zhang US Patent 11,005,503, 2021 | 8 | 2021 |
| Bit-Flipping LDPC decoding algorithm with hard channel information NK Abhiram Prabhakar, Chenrong Xiong, Fan Zhang, Aman Bhatia, HongChich Chou US Patent 10,148,287, 2018 | 8 | 2018 |
| Bit-flipping LDPC decoding algorithm with hard channel information C Xiong, F Zhang, A Bhatia, A Prabhakar, HC Chou, N Kumar US Patent 10,148,287, 2018 | 8 | 2018 |
| Bit-flipping LDPC decoding algorithm with hard channel information C Xiong, F Zhang, A Bhatia, A Prabhakar, HC Chou, N Kumar US Patent 10,148,287, 2018 | 8 | 2018 |
| A VLSI implementation of a FEC decoding system for DTMB (GB20600–2006) standard Y Zhong, H Yang, A Prabhakar 2007 7th International Conference on ASIC, 926-929, 2007 | 8 | 2007 |
| Min-sum decoding for LDPC codes A Bhatia, N Kumar, A Prabhakar, C Xiong, F Zhang US Patent 10,680,647, 2020 | 7 | 2020 |
| VSS LDPC decoder with improved throughput for hard decoding A Prabhakar, J Yen, NY Chu US Patent 10,122,382, 2018 | 7 | 2018 |
| Low-complexity LDPC encoder C Xiong, F Zhang, A Bhatia, A Prabhakar, Y Cai, N Kumar US Patent 10,389,383, 2019 | 6 | 2019 |
| A Study on Effect of Trazadone, Amoxapine and Venlafaxine on MES (Maximal Electroshock_ Induced Seizures in Albino Rates CG Gokul, R Santosh, A Acharya, A Prabhakar, NM Kumar, SR Reshma Pharmacologyonline 3, 214-221, 2011 | 6 | 2011 |
| Memory system with on-the-fly error detection and termination and operating method thereof F Zhang, C Xiong, A Prabhakar, A Bhatia, Y Cai, N Kumar US Patent 10,484,008, 2019 | 5 | 2019 |
| Multistage LDPC encoding L Zeng, A Prabhakar, KM Ng, Y Kou US Patent 8,448,041, 2013 | 3 | 2013 |
| Memory system with shared buffer architecture for multiple decoders and method of operating such memory system J Yen, NY Chu, A Prabhakar US Patent 10,671,323, 2020 | 1 | 2020 |
