Follow
Azeez Bhavnagarwala
Azeez Bhavnagarwala
Metis Microsystems
Verified email at metismicro.com - Homepage
Title
Cited by
Cited by
Year
The impact of intrinsic device fluctuations on CMOS SRAM cell stability
AJ Bhavnagarwala, X Tang, JD Meindl
IEEE journal of Solid-state circuits 36 (4), 658-665, 2001
9062001
Fluctuation limits & scaling opportunities for CMOS SRAM cells
A Bhavnagarwala, S Kosonocky, C Radens, K Stawiasz, R Mann, Q Ye, ...
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005
2142005
A sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing
AJ Bhavnagarwala, S Kosonocky, C Radens, Y Chan, K Stawiasz, ...
IEEE Journal of Solid-State Circuits 43 (4), 946-955, 2008
1432008
The impact of gate-oxide breakdown on SRAM stability
R Rodriguez, JH Stathis, BP Linder, S Kowalczyk, CT Chuang, RV Joshi, ...
IEEE Electron Device Letters 23 (9), 559-561, 2002
1372002
A minimum total power methodology for projecting limits on CMOS GSI
AJ Bhavnagarwala, BL Austin, KA Bowman, JD Meindl
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (3), 235-251, 2000
1022000
Method, system and device for complementary non-volatile memory device operation
A Bhavnagarwala, RC Aitken, L Shifren
US Patent 9,589,636, 2017
942017
Digital logic with reduced leakage
AJ Bhavnagarwala, S Kim, DR Knebel, SV Kosonocky
US Patent 6,977,519, 2005
612005
A transregional CMOS SRAM with single, logic V/sub DD/and dynamic power rails
AJ Bhavnagarwala, SV Kosonocky, SP Kowalczyk, RV Joshi, YH Chan, ...
2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2004
612004
A pico-joule class, 1 GHz, 32 KByte/spl times/64 b DSP SRAM with self reverse bias
AJ Bhavnagarwala, SV Kosonocky, M Immediato, D Knebel, AM Haen
2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2003
542003
Low-power circuits and technology for wireless digital systems
SV Kosonocky, AJ Bhavnagarwala, K Chin, GD Gristede, AM Haen, ...
IBM Journal of Research and Development 47 (2.3), 283-298, 2003
502003
Dynamic-threshold CMOS SRAM cells for fast, portable applications
AJ Bhavnagarwala, A Kapoor, JD Meindl
Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No …, 2000
502000
Circuits and methods for characterizing random variations in device characteristics in semiconductor integrated circuits
A Bhavnagarwala, DJ Frank, SV Kosonocky
US Patent 8,214,169, 2012
422012
Circuit and method for configurable impedance array
AJ Bhavnagarwala, V Chandra, BT Cline
US Patent 9,773,550, 2017
322017
Method, system and device for complementary non-volatile memory device operation
A Bhavnagarwala, RC Aitken
US Patent 9,548,118, 2017
322017
Suppression of leakage currents in VLSI logic and memory circuits
RV Joshi, LL Hsu, AJ Bhavnagarwala
US Patent 6,683,805, 2004
302004
Loadless NMOS four transistor dynamic dual Vt SRAM cell
A Bhavnagarwala, RV Joshi, SV Kosonocky
US Patent 6,920,061, 2005
282005
The impact of stochastic dopant and interconnect distributions on gigascale integration
JD Meindl, VK De, DS Wills, JC Eble, X Tang, JA Davis, B Austin, ...
1997 IEEE International Solids-State Circuits Conference. Digest of …, 1997
261997
Method, system and device for non-volatile memory device operation
AJ Bhavnagarwala, V Asthana, P Agarwal, A Kumar, L Shifren
US Patent 9,947,402, 2018
232018
Self-timed read and write assist and restore circuit
AJ Bhavnagarwala, SV Kosonocky, RV Joshi
US Patent 6,788,566, 2004
232004
Decode path gated low active power SRAM
A Bhavnagarwala, SV Kosonocky
US Patent 6,876,595, 2005
212005
The system can't perform the operation now. Try again later.
Articles 1–20