| Analyzing static and dynamic write margin for nanometer SRAMs J Wang, S Nalam, BH Calhoun Proceedings of the 2008 international symposium on Low Power Electronics …, 2008 | 247 | 2008 |
| Impact of circuit assist methods on margin and performance in 6T SRAM RW Mann, J Wang, S Nalam, S Khanna, G Braceras, H Pilo, BH Calhoun Solid-State Electronics 54 (11), 1398-1407, 2010 | 74 | 2010 |
| A 23.6-Mb/mm SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications Z Guo, D Kim, S Nalam, J Wiedemer, X Wang, E Karl IEEE Journal of Solid-State Circuits 54 (1), 210-216, 2018 | 66 | 2018 |
| 17.1 a 0.6 v 1.5 ghz 84mb sram design in 14nm finfet cmos technology E Karl, Z Guo, JW Conary, JL Miller, YG Ng, S Nalam, D Kim, J Keane, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 63 | 2015 |
| 5.6 Mb/mm 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 … JP Kulkarni, J Keane, KH Koo, S Nalam, Z Guo, E Karl, K Zhang IEEE Journal of Solid-State Circuits 52 (1), 229-239, 2016 | 58* | 2016 |
| A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS technology with capacitive charge-sharing write assist circuitry E Karl, Z Guo, J Conary, J Miller, YG Ng, S Nalam, D Kim, J Keane, ... IEEE Journal of Solid-State Circuits 51 (1), 222-229, 2015 | 53 | 2015 |
| 5T SRAM with asymmetric sizing for improved read stability S Nalam, BH Calhoun IEEE journal of solid-state circuits 46 (10), 2431-2442, 2011 | 52 | 2011 |
| Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T S Nalam, BH Calhoun 2009 IEEE Custom Integrated Circuits Conference, 709-712, 2009 | 48 | 2009 |
| Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation S Nalam, V Chandra, C Pietrzyk, RC Aitken, BH Calhoun 2010 11th International Symposium on Quality Electronic Design (ISQED), 139-146, 2010 | 26 | 2010 |
| Limits of bias based assist methods in nano-scale 6T SRAM RW Mann, S Nalam, J Wang, BH Calhoun 2010 11th International Symposium on Quality Electronic Design (ISQED), 1-8, 2010 | 25 | 2010 |
| Improving SRAM Vmin and yield by using variation-aware BTI stress J Wang, S Nalam, Z Qi, RW Mann, M Stan, BH Calhoun IEEE Custom Integrated Circuits Conference 2010, 1-4, 2010 | 22 | 2010 |
| Virtual prototyper (ViPro) an early design space exploration and optimization tool for SRAM designers S Nalam, M Bhargava, K Mai, BH Calhoun Proceedings of the 47th Design Automation Conference, 138-143, 2010 | 17 | 2010 |
| Dynamic write limited minimum operating voltage for nanoscale SRAMs S Nalam, V Chandra, RC Aitken, BH Calhoun 2011 Design, Automation & Test in Europe, 1-6, 2011 | 16 | 2011 |
| Memory with improved read stability V Chandra, SV Nalam, C Pietrzyk, RC Aitken US Patent 8,339,876, 2012 | 14 | 2012 |
| A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes S Nalam, M Bhargava, K Ringgenberg, K Mai, BH Calhoun 2009 IEEE International Conference on Computer Design, 523-528, 2009 | 13 | 2009 |
| Benton H RW Mann, J Wanga, S Nalam, S Khanna, G Braceras, H Pilo Calhoun a “Impact of circuit assist methods on margin and performance in 6T …, 2010 | 5 | 2010 |
| Sub-550mV SRAM design in 22nm FinFET low power (22FFL) technology with self-induced collapse write assist D Kim, J Wiedemer, P Kolar, A Shrivastava, J Shah, S Nalam, G Baek, ... 2018 IEEE Symposium on VLSI Technology, 151-152, 2018 | 3 | 2018 |
| Circuit and CAD Solutions for Optional SRAM Design in Nanoscale CMOS SV Nalam University of Virginia, 2011 | 1 | 2011 |
| Pipelined Non-strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories S Khanna, SV Nalam, BH Calhoun 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | | 2014 |
| ISSCC 2018/SESSION 11/SRAM/11.1 Z Guo, D Kim, S Nalam, J Wiedemer, X Wang, E Karl | | |
