| Heterojunction bipolar transistors using Si-Ge alloys SS Iyer, GL Patton, JMC Stork, BS Meyerson, DL Harame IEEE Transactions on Electron Devices 36 (10), 2043-2064, 1989 | 550 | 1989 |
| Light emission from silicon SS Iyer, YH Xie Science 260 (5104), 40-46, 1993 | 502 | 1993 |
| Monte Carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go? Laux, Fischetti 1992 International Technical Digest on Electron Devices Meeting, 553-556, 1992 | 428 | 1992 |
| Semiconductor chip having both compact memory and high performance logic PD Agnello, BA Chen, SW Crowder, R Divakaruni, SS Iyer, D Sinitsky US Patent 6,686,617, 2004 | 408 | 2004 |
| Growth and strain compensation effects in the ternary Si1−x−yGexCy alloy system K Eberl, SS Iyer, S Zollner, JC Tsang, FK LeGoues Applied physics letters 60 (24), 3033-3035, 1992 | 397 | 1992 |
| Silicon-germanium base heterojunction bipolar transistors by molecular beam epitaxy GL Patton, SS Iyer, SL Delage, S Tiwari, JMC Stork IEEE Electron Device Letters 9 (4), 165-167, 1988 | 337 | 1988 |
| Method of making 3D integrated circuits MG Farooq, SS Iyer, SJ Koester, H Zhu US Patent 8,158,515, 2012 | 316 | 2012 |
| Single-etch stop process for the manufacture of silicon-on-insulator wafers SS Iyer, E Baran, ML Mastroianni, RA Craven US Patent 5,937,312, 1999 | 301 | 1999 |
| Substrate for tensilely strained semiconductor BA Ek, SS Iyer, PM Pitner, AR Powell, MJ Tejwani US Patent 5,461,243, 1995 | 288 | 1995 |
| Electrically programmable fuse (eFUSE) using electromigration in silicides C Kothandaraman, SK Iyer, SS Iyer IEEE Electron Device Letters 23 (9), 523-525, 2002 | 279 | 2002 |
| New approach to the growth of low dislocation relaxed SiGe material AR Powell, SS Iyer, FK LeGoues Applied physics letters 64 (14), 1856-1858, 1994 | 266 | 1994 |
| 3D integrated circuit device fabrication with precisely controllable substrate removal MG Farooq, R Hannon, SS Iyer, SJ Koester, S Purushothaman, RY Roy US Patent 8,129,256, 2012 | 252 | 2012 |
| Three dimensional integrated circuit integration using dielectric bonding first and through via formation last MG Farooq, R Hannon, SS Iyer, ER Kinser US Patent 9,406,561, 2016 | 212 | 2016 |
| Production of substrate for tensilely strained semiconductor BA Ek, SS Iyer, PM Pitner, AR Powell, MJ Tejwani US Patent 5,759,898, 1998 | 204 | 1998 |
| Electrically programmable fuse (efuse): From memory redundancy to autonomic chips N Robson, J Safran, C Kothandaraman, A Cestero, X Chen, ... 2007 IEEE Custom Integrated Circuits Conference, 799-804, 2007 | 198 | 2007 |
| Surface-stress-induced order in SiGe alloy films FK LeGoues, VP Kesan, SS Iyer, J Tersoff, R Tromp Physical review letters 64 (17), 2038, 1990 | 177 | 1990 |
| Sharp profiles with high and low doping levels in silicon grown by molecular beam epitaxy SS Iyer, RA Metzger, FG Allen Journal of Applied Physics 52 (9), 5608-5613, 1981 | 176 | 1981 |
| Synthesis of Si1− yCy alloys by molecular beam epitaxy SS Iyer, K Eberl, MS Goorsky, FK LeGoues, JC Tsang, F Cardone Applied physics letters 60 (3), 356-358, 1992 | 175 | 1992 |
| Heterogeneous integration for performance and scaling SS Iyer IEEE Transactions on Components, Packaging and Manufacturing Technology 6 (7 …, 2016 | 174 | 2016 |
| Growth temperature dependence of interfacial abruptness in Si/Ge heteroepitaxy studied by Raman spectroscopy and medium energy ion scattering SS Iyer, JC Tsang, MW Copel, PR Pukite, RM Tromp Applied physics letters 54 (3), 219-221, 1989 | 169 | 1989 |
C. KothandaramanON SemiconductorVerified email at onsemi.com
